LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY demux IS
	PORT
	(
		sel		: IN 	STD_LOGIC_VECTOR(1 downto 0);
		b,c,d,e	: IN	STD_LOGIC_VECTOR(7 downto 0);
		a		: OUT	STD_LOGIC_VECTOR(7 downto 0)
	);
END demux;

ARCHITECTURE arch_demux OF demux IS
	
BEGIN
	process(b,c,d,e,sel)
	begin
		case sel is
			when "00" =>
				a <= b;
			when "01" =>
				a <= c;
			when "10" =>
				a <= d;
			when "11" =>
				a <= e;
			when others =>
				--
		end case;
	end process;
END arch_demux;